Summary

Daniel is joined by Dr. Debendra Das Sharma, a Senior Fellow and Chief I/O architect in the Data Platforms and Artificial Intelligence Group at Intel. He is a member of the National Academy of Engineering (NAE), Fellow of IEEE, and Fellow of International Academy of AI Sciences. He is a leading expert on I/O subsystem and interface… Read More

Key takeaways

• UCIe has rapidly evolved from planar 2D/2.5D chiplet connectivity (v1.0) to vertical 3D stacking and doubled bandwidth density (v3.0), maintaining full backwards compatibility throughout all generations.
• UCIe 2.0 introduced holistic chiplet manageability—addressing firmware download, field testing, debug, and repair challenges that arise when chiplets cannot be directly probed after packaging.
• Real-world adoption is accelerating: 97% of surveyed designs use UCIe (39% advanced packaging, 58% standard), with server/AI applications representing 53% of usage and 140+ consortium members spanning foundries, cloud providers, automotive, and networking.

Why this matters

UCIe is establishing itself as the PCI Express-equivalent open standard for chiplet interconnects, enabling a composable, multi-vendor chiplet ecosystem that is critical for scaling AI, HPC, and automotive compute performance beyond monolithic die limitations.

Entities

Show notes

Daniel is joined by Dr. Debendra Das Sharma, a Senior Fellow and Chief I/O architect in the Data Platforms and Artificial Intelligence Group at Intel. He is a member of the National Academy of Engineering (NAE), Fellow of IEEE, and Fellow of International Academy of AI Sciences. He is a leading expert on I/O subsystem and interface… Read More

Themes

• artificial-intelligence